On Synthesis of Easily Testable (k, K) Circuits
نویسندگان
چکیده
A (k;K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k;K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k;K) circuits from a special class of Boolean
منابع مشابه
Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1
Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...
متن کاملDesigning of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1
Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...
متن کاملIrredundant sequential machines via optimal logic synthesis
optimal sequential logic synthesis can produce fallv testable nonscan finite state machines. Test generation algorithms can be used It is well known that optimal logic synthesis can ensure fully to remove all the redundancies in sequential machines resulting in testable combinational logic designs. In this paper. we show that fuily testable designs. However. in general. this method requires opt...
متن کاملEasily testable PLA-based finite state machines
the area and timing penalty associated with LSSD techniques are not acceptable to designers. In this paper, we outline a synthesis procedure, which Logic synthesis and minimization techniques can, in beginning from a State Transition Graph description principle, ensure fully and easily testable combinational of a sequential machine, produces an optimized easily and sequential circuit designs. I...
متن کاملSynthesis of robust delay-fault-testable circuits: theory
Correct operation of synchronous digital circuits requires propagation delays of all sensitizable paths in the circuit to be smaller than a speciied limit. Physical defects and processing variations in integrated circuits can aaect the temporal behavior of a circuit without altering the logical behavior. These defects are called delay faults. In order to design, and especially to synthesize, hi...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IEEE Trans. Computers
دوره 52 شماره
صفحات -
تاریخ انتشار 2003